Ferroelectric memory devices, and other types of semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric capacitors (FeCaps) adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FeCap to one of a pair of complimentary bit lines, with the other bit line being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of plate lines and word lines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage where data memory cells include capacitors constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. Although the polarization of each individual dipole is relatively small, the net polarization of several domains, each comprising a number of aligned dipoles, can be large enough for detection using, for example, standard sense amplifier designs. The gross effect of polarization is a nonzero charge per unit area of the ferroelectric capacitor that does not disappear over time.
A plot 10 of the characteristic hysteresis loop for a conventional ferroelectric capacitor is shown in FIG. 1A, and displays the total charge on the ferroelectric capacitor as a function of the applied voltage. Plot 10 illustrates the charge “Q” (Y-axis), and the voltage “V” (X-axis). Remanent charge (Qr), saturation charge (Qs), and coercive voltage (Vc) are three important parameters that characterize the loop. When the voltage across the capacitor is 0V, the capacitor assumes one of the two stable states: “0” 15, or “1” 20. The total charge stored on the capacitor is Qr for a “0” 15 or −Qr for a “1” 20. A “0” can be switched to a “1” by applying a negative voltage pulse across the capacitor. By doing so, the total charge on the capacitor is reduced by 2Qr, a change of charge that can be sensed by the sense amplifier (amp). Similarly, a “1” can be switched back to a “0” by applying a positive voltage pulse across the capacitor, hence restoring the capacitor charge to +Qr.
Characteristic curve segment 25 represents the charge path of a FeCap from a “1” state 20, thru Vcc as charge is applied, and then thru curve segment 30 to the other stable “0” state 15 as the voltage is relaxed to the FeCap. FIG. 1B is the schematic symbol 50 of the FeCap of FIG. 1A with capacitance CFE, while the “+” and “−” signs beside the FeCap symbol represent the applied voltage polarity.
These characteristics are similar in some respects to those of a magnetic core memory cell except for the following: the hysteresis loop of a ferroelectric capacitor does not have sharp transitions around its coercive points: −Vc and +Vc. This reflects a partial switching of electric domains in a ferroelectric capacitor, and further implies that even a voltage level that is half of Vcc can disturb the state of the capacitor. As a result, it is difficult to access a ferroelectric capacitor in a cross-point array without disturbing the capacitors on the same row or column. Thus, many ferroelectric memory (FeRAM) cell designs include an access transistor in series with the FeCap.
Data in a ferroelectric memory cell is read by connecting a reference voltage to a first bit line, connecting the cell capacitor between a complimentary bit line and a plate line signal voltage, and interrogating the cell. There are several techniques to interrogate an FeRAM cell. Two most common interrogation techniques are step sensing and pulse sensing. In both these interrogation techniques, the cell capacitor is coupled to the complimentary bit line by turning ON an access or a pass gate transistor. In the step sensing, the plate line voltage is stepped from ground (Vss) to a supply voltage (Vdd). In the pulse sensing the plate line voltage is pulsed from Vss to Vdd and then back to Vss. This provides a differential voltage on the bit line pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (V“0”) associated with a capacitor programmed to a binary “0” 15 of FIG. 1A, and that of the capacitor programmed to a binary “1” (V“1”) 20 (e.g., about ½ Vcc). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is buffered and applied to a pair of local IO lines.
The transfer of data between the FeRAM, the sense amp circuit, and the local data bit lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device. In a typical ferroelectric memory read sequence, two sense amp bit lines are initially pre-charged to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp bit lines and interrogated. Thereafter, a reference voltage is connected to the remaining sense amp bit line, and a sense amp senses the differential voltage across the bit lines and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”.
In modern memory devices having millions of data cells, there is a continuing need to reduce component sizes and otherwise to conserve circuit area in the device, so as to maximize device density. Accordingly, memory cell layout architectures such as folded bit line configurations have been developed to conserve on the amount of die area needed to implement large scale memories, like 64 megabit or larger devices. Such devices are typically divided internally into blocks, sections, segments, rows and columns. For example, a 64 M device may include 8 blocks of 8 M each, each block may consist of 8 sections of 1 M each, each section may be 32 segments, with each segment containing 512 words or rows of 64 bits or columns per word. When a data word is read, the cell data from the corresponding bit in each column is sensed using 64 individual sense amplifiers associated with the individual data cell columns.
As current trends continue, the need for increased levels of device integration and process scaling has also increased. One consequence of process technology scaling is the need for further lower voltage operation of devices as scaling continues downward. In particular, there is a need for low voltage operation of CMOS circuits. Additionally, future products may require integration of large amounts of on-chip (embedded) memory. However, few memory structures allow low voltage operation.
SRAM and DRAM, for example, have been thoroughly explored. 6-T SRAM generally requires a very “large area” by comparison to DRAM, Flash, or FeRAM. DRAM typically has a high power consumption, which makes DRAM fairly incompatible with the increasing demand for low power applications.
Attempts to scale the dielectric layer of Flash memory have proven to be difficult or impossible to scale due to degradation of the coupling ratio. Although Flash memories are available with “two bits per cell” allowing a 2× density increase with some penalty of increased sensing circuitry area, Flash also requires high voltages for the program and erase memory operations.
As indicated, these memory technologies are not perfect and result in only marginal improvement, and may also be difficult to implement, particularly while scaling down the technologies and the operating voltage in memory devices. Thus, there is a need for improved apparatus and methods for multiple bit data storage and retrieval in ferroelectric memory cells, while operating the cells over a wide voltage range in memory devices.